The present invention relates to the field of clock synchronisation in packet-switched telecommunications networks. More specifically, the present invention relates to a novel clock module for use with the IEEE 1588-2008 protocol standard.
Several synchronisation sensitive applications in packet-switched networks require methods and related devices for distributing a reference time and/or a reference frequency to several nodes across a network. Moreover, several standards have been developed in order to arrive at interoperable solutions.
One such standard is the IEEE 1588-2008, also known as 1588V2, which presents a hierarchical architecture of clocks organised in successive pairs of master and slave across a network. The 1588V2 standard introduces and defines the concepts of a Boundary Clock (BC) and a Transparent Clock (TC). These concepts consist of 1588V2 features which are added onto a network node, the latter being any network element such as an IP router or an Ethernet switch. For the remainder of the present description, a 1588V2 module (e.g. BC) points specifically to the aforementioned features, but globally also include the supporting network elements (e.g. the IP router) which participate in communicating 1588V2 messages to other distant 1588V2 modules.
As both BC and TC are implemented on a network node which consists of multiple communication ports, they should offer multiple PTP (Precision Time Protocol—another name given to the 1588 protocol) ports. The 1588V2 standard does not impose any specific mapping (e.g. one-to-one mapping) between PTP ports and the supporting network node communication ports. This detail is implementation-specific.
Functionally, a BC does not forward a synchronisation signal (e.g. 1588V2 Event messages). Instead, it recovers the time reference (i.e. timescale of the Grand Master clock) locally and then redistributes this reference down the clock hierarchy. Typically, a BC receives, from its peer master clock, a number of synchronisation messages, typically called PTP messages, and uses those messages to synchronise its own clock. In order to distribute the recovered time reference, it then produces new PTP messages, which are transmitted to its slave(s).
One advantage of BCs is that they are involved in what is known as the Best Master Clock Algorithm (BMCA) in order to determine the best candidate master clock, which is elected as the Grand Master (GM) clock and is positioned at the top of the hierarchical clock architecture. This allows for greater flexibility and for automatic reconfiguration of the clock hierarchical. Conversely, the main disadvantage of using BCs is that they are complex in terms of implementation. Moreover, their related noise accumulation effect is a complex process and is still under study in terms of attainable performance.
A TC, on the other hand, simply receives a PTP message from its master, and forwards it on to its slave. Before forwarding the PTP message to its slave however, the TC modifies a correction field of the PTP message to reflect the time it took for the PTP message, encapsulated within a packet, to transit the TC.
There are several advantages to using TCs. For example, TCs are relatively simple and efficient when compared to BCs (e.g. generally lower noise). On the other hand, TCs do provide some disadvantages as well. One important example of this is that the use of TCs can lead to the infringement of protocol specifications and/or protocol layer separation principles. This is because a TC modifies the header of a PTP message within packet payload, and this, despite the fact that it is not recognized as the destination node of the packet. This is known as “layer violation”.
Whilst the 1588V2 standard has initially specified both types of clock, these technologies are increasingly being perceived as rivals and competing pressures are being put on industrial and research entities to try and promote one or the other.
WO 2008/051123 A1 discloses a method for clock synchronization, wherein the timestamp is updated within a packet.
US 2008/075217 A1 teaches to modify the timestamp in an original synchronization packet on the fly when it passes through either one of the standard interface converters (SIC).
US 2004/258097 A1 discloses passing on a received synchronization telegram to the next node in a cascade structure, wherein each node adds a measure of delay times occurred in the transmission to and processing at that node into the existing signal.